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Project - Design of Fast Speed UART(Universal ASynchronous Receiver

Transmitter).

 

 

Device Target - Xilinx Spartan 3 FPGA (xc3s200-4ft-256).

Language      -  VHDL Or Verilog.

Tools         - Xilinx 8.2i , Leonardo Spectrum, Modelsim 5.1 PE.

Tenure       - 4 Months.

 

 Design Process  ----

 

        1. SRS  -- System Requirement Specification.

        2. Design Partioning.

        3. HDL Behavioural Coding.

        4. Functional Verification.

        5. RTL Coding.

        6. Design Synthesis.

        7. Timing Simulation.

        8. Static Time Analysis.

        9. Dynamic Time Analysis.

        10. Timing and Area And Pin Constraints.

        11. Translating the design in Libraries.

        12. Mapping of Design.

        13. Placement of Cells And Routing The Signals (PAR).

        14. Programming File Generation.

        15. JTAG(Joint Test Action Group) Configuration.

        16. Burning The Device.

        17. H/W Verification.

 

Design Objective  -- This design is an integral unit of a MODEM which

facilitates the Asynchronous Transmission and Reception

                    of the data. This takes care of the Serial data Communication

between two Micro Controllers or between

                     Master and Slave Devices. This Design can be

implemented to facilitate the benefits of I2c Protocol.

 

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